This invention relates to application-specific integrated circuits (“ASICs”), and more particularly to the type of ASICs that are sometimes known as structured ASICs.
So-called structured ASICs are sometimes used as alternatives to programmable logic devices (“PLDs”) such as field-programmable gate arrays (“FPGAs”). An FPGA has a generic structure that may include many identical blocks of logic circuitry, many registers, and a number of other types of circuit blocks such as RAM blocks, DSP blocks, PLL/DLL blocks, etc. These various circuitries are programmable to perform any of a variety of tasks. An FPGA also has a generic interconnection structure. This structure is programmable to interconnect the other circuitries on the device in any of many different ways. The logic blocks of such an FPGA may be referred to as logic elements, logic modules, adaptive logic elements, or adaptive logic modules (“LEs”, “LMs”, “ALEs”, or “ALMs”).
A known type of structured ASIC equivalent to an FPGA has a generic structure that includes many identical instances of a relatively simple circuit block (a so-called hybrid logic element or “HLE”). The structured ASIC may also generically include other blocks that are comparable to the special-purpose blocks on a related FPGA (e.g., RAM blocks, DSP blocks, PLL/DLL blocks, etc.). These generic attributes of the structured ASIC are embodied in several of the masks used to make the ASIC. These masks can therefore be the same or substantially the same for all ASICs of this general kind, and they give the ASIC its “structure.” Other masks (but only some of the total mask set) are customized to give the structured ASIC particular functionality that is equivalent to the functionality of a related, programmed FPGA. For example, these customized masks may configure an HLE or a small group or cluster of HLEs (a complex HLE or “CHLE”) to perform functions equivalent to those performed by an ALE in the related programmed FPGA. Similarly, the customized masks may configure a CHLE to perform functions equivalent to a register in the related programmed FPGA. The customized masks may also provide interconnections between HLEs, CHLEs, and/or other circuit blocks on the ASIC. These interconnections will typically include interconnections equivalent to those provided by the programmable interconnection resources of the related programmed FPGA.
Using a structured ASIC of this kind and in this way has a number of advantages. For example, only some of the ASIC masks need to be customized. This tends to reduce ASIC cost and to speed up the ASIC design/production cycle. It also reduces the risk of a design flaw in the ASIC, and it facilitates producing an ASIC that is a close operational equivalent to the related programmed FPGA (e.g., pin-for-pin identity, timing identity or near identity, etc.). Another advantage of this approach is that it tends to allow the ASIC to include less circuitry (including less circuitry for normal operations) than the related FPGA. This is so because only as many ASIC HLEs as necessary are devoted to performing the functions of each FPGA ALE, and in almost all FPGAs many ALEs are less than fully utilized.
Efficient and reliable conversion from FPGA designs to structured ASIC designs (and vice versa) is facilitated by using known (“library”) conversions from FPGA circuit block functions to ASIC HLE/CHLE functions. This is especially true for FPGA ALE to ASIC HLE/CHLE conversions. The typical FPGA ALE is programmable to perform any of an enormous number of functions. It would therefore be desirable to accumulate in a library solutions that have been worked out for converting as many such FPGA ALE functions as it is reasonably possible to accumulate. Inclusion of an FPGA ALE function conversion in the library avoids the possible need, in the future, to implement that function in a possibly inefficient way, such as by having to break it down for implementation using several HLEs and/or CHLEs that must be interconnected using the “more expensive” global interconnection resources of the ASIC. This would be less efficient than being able to implement the function in one CHLE, for example, in which the HLEs can all be interconnected using “less expensive” local interconnection resources of the ASIC.